Mixed-Signal and Formal Verification

This course provides an in-depth exploration of mixed-signal simulation techniques and formal verification processes, crucial for designing and verifying integrated circuits that include both analog and digital components. Learners will learn to navigate the complexities of mixed-signal environments using advanced simulation tools and methodologies. Practical sessions will include hands-on exercises with industry-standard tools like SPICE (Setting, Perspective, Intervention, Comparison and Evaluation) and Verilog-Analog Mixed-Signal, enhancing the theoretical knowledge with real-world application.

Additionally, the course delves into the principles of formal verification, a rigorous approach to ensure the correctness of circuits through mathematical methods. The curriculum is designed to equip learners with the skills to perform formal verification effectively, addressing common challenges and utilizing best practices to achieve reliable and robust circuit designs. Through lectures, case studies, and project-based learning, learners will gain a comprehensive understanding of how to employ these advanced verification techniques in modern circuit design.

What You'll Learn

Learners will acquire advanced knowledge in running mixed-signal simulation and performing exhaustive design verification. The course covers key topics such as behavioral modeling of analog and digital components, co-simulation strategies, and the integration of analog and digital signal processing. Learners will explore various formal techniques such as equivalence checking, property checking, and assertion-based verification, focusing on how these methods can be applied to mixed-signal circuits.

At the end of the course, learners will be able to:

• Describe the roles of Verilog-A and Verilog-Analog Mixed-Signal in defining analog circuit behavior
• Explain modelling of voltage source, current source, applying threshold, and combining resultant Booleans into an integer
• Explain modelling of digital buses in Verilog-A
• Apply appropriate methodology to run simulation with Analog-top or Digital-top
• Explain modelling of real numbers and Analogue to Digital Converter and Digital to Analogue Converter
• Demonstrate understanding of exhaustive formal verification
• Identify designs suitable for Formal engines
• Explain the differences in interpretation of SystemVerilog Assertions for Formal vs Simulation
• Explain writing constraints via assume properties and assert properties
• Describe and explain writing cover properties
• Assess suitability of various apps in Formal
• Describe the use of implication, replication, consecutive and non-consecutive repetition operators
• Explore availability of Assertion Intellectual Properties (AIPs) for common protocols
• Use Formal Scoreboard to catch data loss, data reordering and data duplication

Minimum Entry Requirement

This programme is suitable for learners who wish to join or progress within the Engineering Services in the manufacturing/digital electronics industry. Prior knowledge in basic electronics and circuit theories, and in at least one programming language will be an advantage.